The invention relates to a circuit arrangement for bit rate adjustment of two digital signals, comprising:
a buffer memory for writing a first signal and reading out a second signal,
a subtractor for forming a difference signal by determining the difference between the counts of a read counter used for controlling the read operation and a write counter used for controlling the write operation, and
a justification decision circuit for generating a stop signal for the read counter.
Such a circuit arrangement for bit rate adjustment of two digital signals is necessary in information transmission technology, for example, in plesiochronous multiplexers which combine plesiochronous signals. Two digital signals are called plesiochronous when their bit rates deviate from a nominal value within a given tolerance. Before plesiochronous signals are combined by a plesiochronous multiplexer, they are all to be brought to the same bit rate. This bit rate difference is eliminated in that stuff bits are inserted at fixed instants into the signal having the higher bit rate. The signal having the higher bit rate is then structured in a frame. Such a frame may be, for example, the so-called Synchronous Transport Module STM-N (cf. CCITT Recommendations G707, G708, G709). Such a frame is partitioned into rows and each row again contains a specific number of bytes. This frame contains justification locations for variable stuff bits in addition to the justification locations for fixed stuff bits. The justification locations for fixed stuff bits are generally filled with stuff bits, whereas the locations for the variable stuff bits are filled either with information bits or stuff bits. With the positive justification (positive stuffing) technique an information bit or a stuff bit is inserted at a justification location for a variable stuff bit. With the positive/negative justification (negative stuffing) technique an information bit is additionally inserted at a location for a fixed stuff bit as required. A justification decision circuit in the circuit arrangement for bit rate adjustment decides whether a stuff bit or an information bit is to be inserted at a justification location. Because fixed locations in the frames are provided for the stuff bits, these bits can again be removed on demultiplexing. Information about whether a variable stuff bit has been inserted at a justification location can still be transmitted along with the signal having the higher bit rate.
On the receiving side of the transmission system a plesiochronous demultiplexer can be followed by a corresponding circuit arrangement for removing the stuff bits and bringing the bit rate back to its original value. Removing the stuff bits is effected via a buffer memory in which only useful dam are written. The reading operation is controlled by a phase-locked loop so that a clock frequency which is as uniform as possible (having little jitter) is generated. Jitter is understood to mean the deviation of the clock edges from their nominal locations. High-frequency spectral portions in the jitter may be reduced on the receiving side by the low-pass filtering property of the phase-locked loop. However, low-frequency spectral components of the jitter may arise as a result of stuffing. The amplitude of the low-frequency spectral components can only be reduced by means of stuffing i.e. in the circuit arrangement for bit rate adjustment (sending side).
The circuit arrangement mentioned above is known from German Patent Application P 40 18 539, to which copending U.S. patent application Ser. No. 07/711239 corresponds. That circuit arrangement comprises a buffer memory to which a first signal is applied by an input circuit. The input circuit comprises a code converter and a phase-locked loop with incorporated frequency dividers connected thereto. In the code converter the received signal is converted into a binary code and applied to the buffer memory as a first signal. By means of the phase-locked loop and the linked frequency dividers a bit clock signal and clock signals having a higher frequency are produced. The writing in the buffer memory is controlled by a write counter which applies write addresses to the buffer memory with each bit clock signal. The reading from the buffer memory is controlled by a read counter producing read addresses. The counts of the write and read counters are applied to a subtractor which subtracts the count of the read counter from that of the write counter. For a refinement of the result of the subtraction also the higher-frequency clock signals of the phase-locked loop with linked dividers are applied to the subtractor. The result of the subtraction is applied as a difference signal to a justification decision circuit which produces a stop signal for the read counter and justification information signals. The justification decision circuit comprises an adder circuit which receives the difference signal, the adder output signal delayed by one frame in a delay element, and justification signals. A justification signal comprises the information about whether negative or positive stuffing is to be used. A threshold detector following in the circuit after the summing element decides whether a negative or positive stuff bit is to be generated. 0n the basis of this information from the threshold detector it is decided in a combining circuit whether the read counter is stopped or continues to receive a read clock signal. The adder circuit and the delay element are used for reducing the amplitude of the low-frequency spectral components of the jitter.